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9UMS9001 idt ? pc main clock - ck540 1247b?07/19/10 pc main clock - ck540 1 recommended application: features/benefits: calistoga based ultra-mobile pc (umpc) ? supports dothan ulv cpus with 100 and 133 mhz cpu outputs ? dedicated test/sel and test/mode pins saves isolation resistors on pins ? pci_src and cpu stop inputs for power manangment ? fully integrated vreg ? integrated series resistors on differential outputs ? supports split rail operation for maximum power savings ? also runs from single 3.3v rail ? 1.05v-3.3v support for differential vddio pin configuration output features: ? 2 - cpu low power differential push-pull pairs ? 1 - itp low power differential push-pull pair ? 4 - src low power differential push-pull pairs ? 1 - lcd100 sscd low power differential push-pull pair ? 1 - dot96 low power differential push-pull pair ? 3 - pci, 33mhz ? 1 - usb, 48mhz ? 1 - ref, 14.31818mhz gndref fslc ck_pwrgd#/pd vddcpupll_3.3 cpu0t_lprs cpu0c_lprs gndcpu vddio_cpu cpu1t_lprs cpu1c_lprs cpuitpt_lprs cpuitpc_lprs cpu_stop# fslb 56 55 54 53 52 51 50 49 48 47 46 45 44 43 x2 1 42 clkreq2# x1 2 41 clkreq3# vddrefio_3.3 3 40 vddcore_3.3 ref0 4 39 src3t_lprs sdata 538 src3c_lprs sclk 6 37 src2t_lprs test_sel 7 36 src2c_lprs test_mode 8 35 vddio_src pci_stop# 9 34 gndsrc vddio_pci3.3 10 33 src1t_lprs pci0 11 32 src1c_lprs pci1 12 31 src0t_lprs pci_f2 13 30 src0c_lprs gndpci 14 29 cklreq0# 15 16 17 18 19 20 21 22 23 24 25 26 27 28 gnd48 usb_48mhz vdd48io_3.3 vdd48pll_3.3 vddio_96mhz dot96c_lprs dot96t_lprs gnd gnd lcd100c_lprs lcd100t_lprs vddio_lcd vddlcdpll_3.3 clkreq1# 56-pin mlf ics9UMS9001
idt ? pc main clock - ck540 1247b?07/19/10 advance information 9UMS9001 pc main clock - ck540 2 pin description pin # pin name type description 1 x2 out crystal output, nominally 14.318mhz. 2 x1 in crystal input, nominally 14.318mhz. 3 vddrefio_3.3 pwr power pin for the ref output and crystal oscillator. 3.3v nominal. 4 ref0 out 3.3v 14.318mhz reference clock 5 sdata i/o data pin for smbus circuitry, 5v tolerant. 6 sclk in clock pin of smbus circuitry, 5v tolerant. 7test_sel in 3.3v input that puts the part in test mode. this is a realtime input. see the test clarification table for details. 8 test_mode in when test mode is selected, this chooses either hi-z or ref/n for the outputs. 9 pci_stop# in 3.3v tolerant input that stops all pci and src clocks, except those set to be free running. 10 vddio_pci3.3 pwr 3.3v power supply for the pci outputs 11 pci0 out 3.3v pci clock output. 12 pci1 out 3.3v pci clock output. 13 pci_f2 out free running 3.3v pci clock output 14 gndpci pwr ground for pci output clocks. 15 gnd48 pwr ground for the usb clock. 16 usb_48mhz out fixed 3.3v 48mhz usb clock output 17 vdd48io_3.3 pwr 3.3v power supply for the 48mhz output 18 vdd48pll_3.3 pwr 3.3v power supply for the 48/96mhz pll 19 vddio_96mhz pwr power supply for dot96 output. vdd_io = 1.05 to 3.3v +/-5%. 20 dot96c_lprs out complement side of low-power ck505-type 96mhz differential clock. rs is integrated (no external series resistor required). 21 dot96t_lprs out true side of low-power ck505-type 96mhz differential clock. rs is integrated (no external series resistor required). 22 gnd pwr ground for 96mhz output 23 gnd pwr ground for lcd 100 mhz output. 24 lcd100c_lprs out complement side of low-power ck505-type lcd100mhz spreading differential clock. rs is integrated (no external series resistor required). 25 lcd100t_lprs out true side of low-power ck505-type lcd100mhz spreading differential clock. rs is integrated (no external series resistor required). 26 vddio_lcd pwr power supply for lcd100 output. vdd_io = 1.05 to 3.3v +/-5%. 27 vddlcdpll_3.3 pwr 3.3v power supply for the lcd100 spreading pll 28 clkreq1# in clock request input for src output pair 1. see the src, lcd, dot power management table for details
idt ? pc main clock - ck540 1247b?07/19/10 advance information 9UMS9001 pc main clock - ck540 3 pin description (continued) pin # pin name type description 29 cklreq0# in clock request input for src output pair 0. see the src, lcd, dot power management table for details 30 src0c_lprs out complement side of low-power ck505-type src0 differential clock. rs is integrated (no external series resistor required). 31 src0t_lprs out true side of low-power ck505-type src0 differential clock. rs is integrated (no external series resistor required). 32 src1c_lprs out complement side of low-power ck505-type src1 differential clock. rs is integrated (no external series resistor required). 33 src1t_lprs out true side of low-power ck505-type src1 differential clock. rs is integrated (no external series resistor required). 34 gndsrc pwr ground for src clocks 35 vddio_src pwr power supply for src outputs. vdd_io = 1.05 to 3.3v +/-5%. 36 src2c_lprs out complement side of low-power ck505-type src2 differential clock. rs is integrated (no external series resistor required). 37 src2t_lprs out true side of low-power ck505-type src2 differential clock. rs is integrated (no external series resistor required). 38 src3c_lprs out complement side of low-power ck505-type src3 differential clock. rs is integrated (no external series resistor required). 39 src3t_lprs out true side of low-power ck505-type src3 differential clock. rs is integrated (no external series resistor required). 40 vddcore_3.3 pwr 3.3v power supply for 3.3v core 41 clkreq3# in clock request input for src output pair 2. see the src, lcd, dot power management table for details 42 clkreq2# in clock request input for src output pair 2. see the src, lcd, dot power management table for details 43 fslb in low threshold frequency select input. see table 1: cpu frequency select table and the vih_fs and vil_fs specifications. 44 cpu_stop# in stops all cpu clocks except those set to be free running. 45 cpuitpc_lprs out complement side of low-power ck505-type cpuitp differential clock. rs is integrated (no external series resistor required). note that this pin is not muxed with an src output. 46 cpuitpt_lprs out true side of low-power ck505-type cpuitp differential clock. rs is integrated (no external series resistor required). 47 cpu1c_lprs out complement side of low-power ck505-type cpu1 differential clock. rs is integrated (no external series resistor required). note that this pin is not muxed with an src output. 48 cpu1t_lprs out true side of low-power ck505-type cpu1 differential clock. rs is integrated (no external series resistor required). 49 vddio_cpu pwr power supply for cpu outputs. vdd_io = 1.05 to 3.3v +/-5%. 50 gndcpu pwr ground pin for cpu outputs 51 cpu0c_lprs out complement side of low-power ck505-type cpu1 differential clock. rs is integrated (no external series resistor required). note that this pin is not muxed with an src output. 52 cpu0t_lprs out true side of low-power ck505-type cpu1 differential clock. rs is integrated (no external series resistor required). 53 vddcpupll_3.3 pwr 3.3v power supply for cpu pll. 54 ck_pwrgd#/pd in notifies 9UMS9001 to sample latched inputs or enter power down mode. 1 = power down mode falling edge = sample latched inputs 0 = normal operation 55 fslc in low threshold frequency select input. see table 1: cpu frequency select table and the vih_fs and vil_fs specifications. 56 gndref pwr ground pin for crystal oscillator circuit and ref output
idt ? pc main clock - ck540 1247b?07/19/10 advance information 9UMS9001 pc main clock - ck540 4 functional block diagram power groups osc cpu/src/ pc ss-pll lcd ss pll fixed exact 48mhz control logic x1 ref pci src(3:0) cpu(2:0) lcd dot96mh z 48mhz x2 fslc fslb ckpwrgd#/pd pci_stop# cpu_stop# clkreq(3:0)# itp_en testsel testmode vdd3.3v vddio 1.05~3.3v gnd 49 low power outputs 53 analog 53 35 low power outputs 40 analog 26 low power outputs 27 pll 19 22 dot 96mhz low power outputs 17, 18 15 3 56 10 14 xtal, ref pciclk srcclk lcdclk description master clock, analog usb 48 23 34 cpuclk 50 pin number
idt ? pc main clock - ck540 1247b?07/19/10 advance information 9UMS9001 pc main clock - ck540 5 table 1: cpu frequency select table fs l c 1 b0b7 fs l b 1 b0b6 cpu mhz src mhz pci mhz ref mhz u sb mhz dot mhz 0 0 133.33 01reserved 1 0 100.00 1 1 200.00 1. fs l c is a low-threshold input.please see v il_fs and v ih_fs spec ific ations in the input/supply/common output parameters table for correct values. also refer to the test clarification table. 100.00 100.00 33.33 33.33 14.318 48.00 96.00 14.318 48.00 96.00 table 3: io_vout select table b5b2 b5b1 b5b0 io_vou t 000 0.3v 001 0.4v 010 0.5v 011 0.6v 100 0.7v 101 0.8v 110 0.9v 111 1.0v table 2: lcd quick configuration pin 24/25 spread mhz % 0 0 0 0 100.00 0.25% down spread lcdclk 0 0 0 1 100.00 0.5% down spread lcdclk 0 0 1 0 100.00 1% down spread lcdclk 0 0 1 1 100.00 1.25% down spread lcdclk 0 1 0 0 100.00 1.5% down spread lcdclk 0 1 0 1 100.00 2% down spread lcdclk 0 1 1 0 100.00 2.5% down spread lcdclk 0 1 1 1 100.00 3.0% down spread lcdclk 1 0 0 0 100.00 0.25% center spread lcdclk 1 0 0 1 100.00 0.5% center spread lcdclk 1 0 1 0 100.00 1% center spread lcdclk 1 0 1 1 100.00 1.25% center spread lcdclk 1 1 0 0 100.00 1.5% center spread lcdclk 1 1 0 1 100.00 2% center spread lcdclk 1 1 1 0 100.00 2.5% center spread lcdclk 1 1 1 1 100.00 3.0% center spread lcdclk b1b3 b1b2 b1b1 comment b1b0
idt ? pc main clock - ck540 1247b?07/19/10 advance information 9UMS9001 pc main clock - ck540 6 absolute maximum ratings parameter symbol conditions min max units notes maximum supply voltage vddxxx_3.3 supply voltage 4.6 v 1,7 maximum supply voltage vddxxx_1.8 supply voltage 2.3 v 1,7 maximum supply voltage vddxxx_io low-voltage differential i/o supply 3.8 v 1,7 maximum input voltage v ih 3.3v lvcmos inputs 4.6 v 1,7,8 minimum input voltage v il any input gnd - 0.5 v 1,7 storage temperature ts - -65 150 c1,7 input esd protection esd prot human body model 2000 v 1,7 electrical characteristics - input/supply/common output parameters parameter symbol conditions min max units notes ambient operating temp tambient - 0 70 c 1 supply voltage vddxxx_3.3 supply voltage 3.135 3.465 v 1 supply voltage vddxxx_1.8 supply voltage 1.71 1.89 v 1 supply voltage vddxxx_io low-voltage differential i/o supply 1.05 3.465 v 1 input high voltage v ihse single-ended inputs 2 v dd + 0.3 v 1 input low voltage v ilse single-ended inputs v ss - 0.3 0.8 v 1 input leakage current i in v in = v dd , v in = gnd -5 5 ua 1 input leakage current i inres inputs with pull or pull down resistors v in = v dd , v in = gnd -200 200 ua 1 output high voltage v ohse single-ended outputs, i oh = -1ma 2.4 v 1 output low voltage v ols e single-ended outputs, i ol = 1 ma 0.4 v 1 output high voltage v ohdi f differential outputs 0.7 0.9 v 1 output low voltage v oldi f differential outputs 0.4 v 1 low threshold input- high voltage (test mode) v ih_fs_test 3.3 v +/-5% 2 v dd + 0.3 v 1 low threshold input- high voltage v ih_fs 3.3 v +/-5% 0.7 1.5 v 1 low threshold input- low voltage v il_fs 3.3 v +/-5% v ss - 0.3 0.35 v 1 operating supply current i dd_default 3.3v supply, lcdpll off 80 ma 1 i dd_lcden 3.3v supply, lcdpll enabled 100 ma 1 i dd_io 0.8v supply, differential io current, all outputs enabled 25 ma 1 i dd_pd3.3 3.3v supply, power down mode 1 ma 1 i dd_pdio 0.8v io supply, power down mode 0.1 ma 1 input frequency f i v dd = 3.3 v 15 mhz 2 pin inductance l p in 7nh1 c in logic inputs 1.5 5 pf 1 c ou t output pin capacitance 6 pf 1 c inx x1 & x2 pins 7 pf 1 spread spectrum modulation frequency f ssmod triangular modulation 30 33 khz 1 power down current input capacitance
idt ? pc main clock - ck540 1247b?07/19/10 advance information 9UMS9001 pc main clock - ck540 7 ac electrical characteristics - input/common parameters parameter symbol conditions min max units notes clk stabiliz ation t stab from vdd power-up or de- assertion of pd# to 1st clock 1.8 ms 1 tdrive_src t drsrc src output enable after pci_stop# de-assertion 15 ns 1 tdrive_pd# t drpd differential output enable after pd# de-assertion 300 us 1 tdrive_cpu t drsrc cpu output enable after cpu_stop# de-assertion 10 ns 1 tfall_pd# t fall 5ns1 trise_pd# t rise 5ns1 fall/rise time of pd#, pci_stop# and cpu_stop# inputs ac electrical characteristics - low power differential outputs parameter symbol conditions min max units notes rising edge slew rate t slr differential measurement 1 4 v/ns 1,2 falling edge slew rate t flr differential measurement 1 4 v/ns 1,2 rise/fall time variation t slvar single-ended measurement 125 ps 1 maximum output voltage v high includes overshoot 1150 mv 1 minimum output voltage v low includes undershoot -300 mv 1 differential voltage swing v swing differential measurement 300 mv 1 crossing point voltage v xabs single-ended measurement 300 550 mv 1,3,4 crossing point variation v xabsvar single-ended measurement 140 mv 1,3,5 duty cycle d cyc differential measurement 45 55 % 1 cpu jitter - cycle to cycle cpuj c2c differential measurement 85 ps 1 src jitter - cycle to cycle srcj c2c differential measurement 125 ps 1 dot jitter - cycle to cycle dotj c2c differential measurement 250 ps 1 cpu[1:0] skew cpu skew10 differential measurement 100 ps 1 cpu[2_itp:0] skew cpu skew20 differential measurement 150 ps 1 src[3:0] skew src skew differential measurement 250 ps 1 electrical characteristics - pciclk/pciclk_f parameter symbol conditions min max units notes long accuracy ppm see tperiod min-max values -300 300 ppm 1,6 33.33mhz output nominal 30.00900 ns 6 33.33mhz output spread 30.15980 ns 6 absolute min/max period t abs 33.33mhz output nominal/spread 29.49100 30.65980 ns 6 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 v oh @min = 1.0 v -33 ma 1 v oh @max = 3.135 v -33 ma 1 v ol @ min = 1.95 v 30 ma 1 v ol @ max = 0.4 v 38 ma 1 rising edge slew rate t slr measured from 0.8 to 2.0 v 1 4 v/ns 1 falling edge slew rate t flr measured from 2.0 to 0.8 v 1 4 v/ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 skew t skew v t = 1.5 v 250 ps 1 intentional pci-pci delay t dela y v t = 1.5 v ps 1,9 jitter, cycle to cycle t j c y c-c y c v t = 1.5 v 500 ps 1 0 nominal clock period 29.99100 t period output high current i oh output low current i ol
idt ? pc main clock - ck540 1247b?07/19/10 advance information 9UMS9001 pc main clock - ck540 8 electrical characteristics - usb48mhz parameter symbol conditions min max units notes long accuracy ppm see tperiod min-max values -100 100 ppm 1,2 clock period t p eriod 48.00mhz output nominal 20.83125 20.83542 ns 2 absolute min/max period t abs 48.00mhz output nominal 20.48130 21.18540 ns 2 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 v oh @min = 1.0 v -29 ma 1 v oh @max = 3.135 v -23 ma 1 v ol @ min = 1.95 v 29 ma 1 v ol @ max = 0.4 v 27 ma 1 rising edge slew rate t slr measured from 0.8 to 2.0 v 1 2 v/ns 1 falling edge slew rate t flr measured from 2.0 to 0.8 v 1 2 v/ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 jitter, cycle to cycle t j c y c-c y c v t = 1.5 v 350 ps 1 output high current i oh i ol output low current electrical characteristics - smbus interface parameter symbol conditions min max units notes smbus voltage v dd 2.7 5.5 v 1 low-level output voltage v ols m b @ i pullup 0.4 v 1 current sinking at v olsmb = 0.4 v i pullup smb data pin 4 ma 1 sclk/sdata clock/data rise time t ri2c (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata clock/data fall time t fi2c (min vih + 0.15) to (max vil - 0.15) 300 ns 1 maximum smbus operating frequency f smbus block mode 100 khz 1
idt ? pc main clock - ck540 1247b?07/19/10 advance information 9UMS9001 pc main clock - ck540 9 notes on electrical characteristics: 1 guaranteed by design and characterization, not 100% tested in production. 2 slew rate measured through vswing centered around differential zero 3 vxabs is defined as the voltage where clk = clk# 4 only applies to the differential rising edge (clk rising and clk# falling) 6 all long term accuracy and clock period specifications are guaranteed assuming that refout is at 14.31818mhz 5 defined as the total variation of all crossing voltages of clk rising and clk# falling. matching applies to rising edge rate of clk and falling edge of clk#. it is measured using a +/-75mv window centered on the average cross point where clk meets clk#. the average cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations 7 operation under these conditions is neither implied, nor guaranteed. 9 see pci clock-to-clock delay figure 8 maximum input voltage is not to exceed maximum vdd electrical characteristics - ref-14.318mhz parameter symbol conditions min max units notes long accuracy ppm see tperiod min-max values -300 300 ppm 1,2 clock period t p eriod 14.318mhz output nominal 69.8203 69.8622 ns 2 absolute min/max period t abs 14.318mhz output nominal 69.8203 70.86224 ns 2 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 output high current i oh v oh @min = 1.0 v, v oh @max = 3.135 v -33 -33 ma 1 output low current i ol v ol @min = 1.95 v, v ol @max = 0.4 v 30 38 ma 1 rising edge slew rate t slr measured from 0.8 to 2.0 v 1 4 v/ns 1 falling edge slew rate t flr measured from 2.0 to 0.8 v 1 4 v/ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 jitter t jcyc-cyc v t = 1.5 v 1000 ps 1
idt ? pc main clock - ck540 1247b?07/19/10 advance information 9UMS9001 pc main clock - ck540 10 general i 2 c serial interface information for the 9UMS9001 how to write: ? controller (host) sends a start bit. ? controller (host) sends the write address d2 (h) ? ics clock will acknowledge ? controller (host) sends the beginning byte location = n ? ics clock will acknowledge ? controller (host) sends the data byte count = x ? ics clock will acknowledge ? controller (host) starts sending byte n through byte n + x -1 (see note 2) ? ics clock will acknowledge each byte one at a time ? controller (host) sends a stop bit how to read: ? controller (host) will send start bit. ? controller (host) sends the write address d2 (h) ? ics clock will acknowledge ? controller (host) sends the begining byte location = n ? ics clock will acknowledge ? controller (host) will send a separate start bit. ? controller (host) sends the read address d3 (h) ? ics clock will acknowledge ? ics clock will send the data byte count = x ? ics clock sends byte n + x -1 ? ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . ? controller (host) will need to acknowledge each byte ? controller (host) will send a not acknowledge bit ? controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack p stop bit x byte index block write operation slave address d2 (h) beginning byte = n write start bit controller (host) byte n + x - 1 data byte count = x beginning byte n t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit slave address d3 (h) index block read operation slave address d2 (h) beginning byte = n ack ack data byte count = x ack ics (slave/receiver) controller (host) x byte ack ack
idt ? pc main clock - ck540 1247b?07/19/10 advance information 9UMS9001 pc main clock - ck540 11 byte 0 fs readback, ss enable, stop control register bit pin name description type 0 1 default 7 - fslc cpu freq. sel. bit msb rw latch 6 fslb cpu freq. sel. bit lsb rw latch 5 cpu_ss_en spread spectrum enable for cpu/src/pci outputs rw ss disabled ss enabled 1 4 lcd_enable turns on lcd pll rw off on 1 3 src3_stop src 3 stop control rw 0 2 src2_stop src 2 stop control rw 0 1 src1_stop src 1 stop control rw 0 0 src0_stop src 0 stop control rw 0 byte 1 lcd quick config and cpu stop controlregister bit pin name description type 0 1 default 7 cpu_itp_stop cpu_itp stop control rw 0 6 cpu1_stop cpu1 stop control rw 1 5 cpu0_stop cpu0 stop control rw 1 4 lcd_ss_en turns on ss for lcd pll rw off on 1 3 lcd_ssc_sel select down or center ssc rw down spread center spread 0 2 lcd_cf2 pll3 quick config bit 2 rw 0 1 lcd_cf1 pll3 quick config bit 1 rw 0 0 lcd_cf0 pll3 quick config bit 0 rw 1 byte 2 output enable and stop control register bit pin name description type 0 1 default 7 pci_f2_stop free running pci stop control rw 0 6 pci1_stop pci1 stop control rw 1 5 pci0_stop pci 0 stop control rw 1 4 ref_oe output enable for ref rw output disabled output enabled 1 3 usb_oe output enable for usb rw output disabled output enabled 1 2 pcif2_oe output enable for pci2 rw output disabled output enabled 1 1 pci1_oe output enable for pci1 rw output disabled output enabled 1 0 pci0_oe output enable for pci0 rw output disabled output enabled 1 byte 3 output enable register bit pin name description type 0 1 default 7 cpu_itp_oe output enable for cpu_itp rw output disabled output enabled 1 6 cpu1_oe output enable for cpu1 rw output disabled output enabled 1 5 cpu0_oe output enable for cpu0 rw output disabled output enabled 1 4 reserved reserved rw 0 3 src3_oe output enable for src4 rw output disabled output enabled 1 2 src2_oe output enable for src4 rw output disabled output enabled 1 1 src1_oe output enable for src4 rw output disabled output enabled 1 0 src0_oe output enable for src4 rw output disabled output enabled 1 byte 4 output enable and clkreq# control register bit pin name description type 0 1 default 7 dot96_oe output enable for dot96 rw output disabled output enabled 1 6 lcd100_oe output enable for lcd100 rw output disabled output enabled 1 5 reserved reserved rw 0 4 reserved reserved rw 0 3 src3_cr src3 clkreq3# enable rw 0 2 src2_cr src2 clkreq2# enable rw 0 1 src1_cr src1 clkreq1# enable rw 0 0 src0_cr src0 clkreq0# enable rw 0 see frequency select table not controlled by clkreq# controlled by clkreq# free running stops with pci_stop# assertion see table 2: lcd quick configuration free running stops with cpu_stop# assertion stops with pci_stop# assertion free running
idt ? pc main clock - ck540 1247b?07/19/10 advance information 9UMS9001 pc main clock - ck540 12 byte 5 drive strength control register bit pin name description type 0 1 default 7 pci_f2 strength sets the pci_f2 output drive strength rw 1 6 pci1 strength sets the pci1 output drive strength rw 1 5 pci0 strength sets the pci0 output drive strength rw 1 4 48mhz strength sets the 48mhz output drive strength rw 1 3 ref strength sets the ref output drive strength rw 2 loads 3 loads 1 2 io_vout2 io output voltage select (most significant bit) rw 1 1 io_vout1 io output voltage select rw 0 0 io_vout0 io output voltage select (least significant bit) rw 1 byte 6 reserved register bit pin name description type 0 1 default 7 reserved reserved rw 0 6 reserved reserved rw 0 5 reserved reserved rw 0 4 reserved reserved rw 0 3 reserved reserved rw 0 2 reserved reserved rw 0 1 reserved reserved rw 0 0 reserved reserved rw 0 byte 7 vendor id/ revision id bit pin name description type 0 1 default 7 rev code bit 3 r x 6 rev code bit 2 r x 5 rev code bit 1 r x 4 rev code bit 0 r x 3 vendor id bit 3 r 0 2 vendor id bit 2 r 0 1 vendor id bit 1 r 0 0 vendor id bit 0 r 1 byte 8 device id register bit pin name description type 0 1 default 7 device_id3 r 0 6 device_id2 r 0 5 device_id1 r 1 4 device_id0 r 1 3 reserved reserved rw 0 2 reserved reserved rw 0 1 reserved reserved rw 0 0 reserved reserved rw 1 byte 9 test mode register bit pin name description type 0 1 default 7 lcd_stop lcd stop control rw free running stops with pci_stop# assertion 0 6 reserved reserved rw 0 5 reserved reserved rw 0 4 test mode select allows test select, ignores test sel input pin rw outputs hi-z outputs = ref/n 0 3 test mode entry enters into test mode, ignores input pin rw normal operation test mode 0 2 reserved reserved rw 0 1 reserved reserved rw 0 0 pll1_ss pll1 spread spectrum mode rw down-spread center-spread 0 revision id vendor id ics is 0001, binary package id code devide id = 0011 hex 56-pin qfn 2 loads see table 3: v_io selection (default is 0.8v) vendor specific 1 load
idt ? pc main clock - ck540 1247b?07/19/10 advance information 9UMS9001 pc main clock - ck540 13 test clarification table comments test_sel hw pin test_mode hw pin test entry bit b9b3 ref/n or hi-z b9b4 output <2.0v x 0 0 normal >2.0v 0 x 0 hi-z >2.0v 0 x 1 ref/n >2.0v 1 x 0 ref/n >2.0v 1 x 1 ref/n <2.0v x 1 0 hi-z <2.0v x 1 1 ref/n b9b3: 1= enter test mode, default = 0 (normal operation) b9b4: 1= ref/n, default = 0 (hi-z) h w s w power-up w/ test_sel = 1 to enter test mode cycle power to disable test mode test_mode -->low vth input test_mode is a real time input if test_sel hw pin is 0 during power-up, test mode can be invoked through b9b3. if test mode is invoked by b9b3, only b9b4 is used to select hi-z or ref/n fslb/test_mode pin is not used. cycle power to disable test mode, one shot control
idt ? pc main clock - ck540 1247b?07/19/10 advance information 9UMS9001 pc main clock - ck540 14 dimensions symbol min. max. a0.81.0 a1 0 0.05 n 56 a3 n d 14 b 0.18 0.3 n e 14 e d x e basic 8.00 x 8.00 d2 min. / max. 4.35 / 4.65 e2 min. / max. 5.05 / 5.35 l min. / max. 0.30 / 0.50 ics 56l tolerance symbol 0.50 basic dimensions 0.25 reference thermally enhanced, very thin, fine pitch quad flat / no lead plastic package e top view or anvil singulation a3 l n (ref.) e e e e (ref. ) (ref. ) (ref. ) (typ.) if a1 even e2 d2 d2 2 a c 0.08 c e2 2 2 2 1 sawn singulation index area seating plane are even thermal base odd b (n - 1)x n 1 chamfer 4x 0.6 x 0.6 max optional d d & & n d n d n e n e & n d n e (n - 1)x e ordering information part / order number shipping package package temperature 9UMS9001aklf tubes 56-pin mlf 0 to +70 c 9UMS9001aklft tape and reel 56-pin mlf 0 to +70 c ?lf? suffix to the part number are the pb-free configuration and are rohs compliant. ?a? is the device revision designator (will not correlate with the datasheet revision).
idt ? pc main clock - ck540 1247b?07/19/10 advance information 9UMS9001 pc main clock - ck540 15 innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support 408-284-6578 pcclockhelp@idt.com corporate headquarters integrated device t echnology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan idt singapore pte. ltd. 1 kallang sector #07-01/06 kolamayer industrial park singapore 349276 phone: 65-6-744-3356 fax: 65-6-744-1764 europe idt europe limited 321 kingston road leatherhead, surrey kt22 7tu england phone: 44-1372-363339 fax: 44-1372-378851 ? 2010 integrated device technology , inc. all rights reserved. product specifications subject to change without notice. idt, ic s, and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa revision history rev. issue date who description page # a 8/28/2008 rdw 1. removed ck505 reference is device id byte of smbus 2. moved smbus after electrical characteristics 3. made data sheet rev a device. 4. move to final 8, 9, 10 b 7/19/2010 rdw 1. corrected pin type for pins 8, 21, 23. 2

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